An Introduction to Array Logic

After a discussion of the reasons for choosing to implement logic in array form. a detailed description of the nature of array logic is given. Topics specifically discussed include general array structures and implementation, influence of decoder partitioning, design of logic arrays, output phase, “split” variables, feedback in logic arrays, and reconfiguration. Introduction Although there will always be a need for logic which offers the best possible performance regardless of cost, most logic necessarily falls into either the cost/performance class or the low cost/marginal performance class, Thus, an important aspect of the logic designer’s job is his constant search for the best possible compromise between performance and unit cost. The kind of curve which determines the designer’s decision is illustrated in Fig. 1. Two important quantities are shown; B, the base or threshold cost that shifts the curve to the right or left, and C, the knee of the curve. In the past, when logic circuits were built of discrete components, or even from small unit logic blocks such as NAND or NOR gates, the knee of the curve was fairly easy to determine. Cost depended directly on the number of components used and, as it turned out, an average of three to six units of delay also coincided with a minimum number of circuits. Fewer levels of delay implied a significant increase in cost whereas adding delay gave little or no cost improvement. The base of the curve, B, was also fairly well defined, being determined by such things as total time spent in design and, to a lesser extent, by the number of different applications for a given cluster of logic. Assembly costs were essentially a function of the number of circuits, whereas the individual components cost he same in whatever circuits they happened to be used. With the advent of large scale integration (LSIj the factors that determine this cost/performance curve have begun to change drastically. To begin with, cost must be considered in terms of total silicon area as opposed to 98 the number of devices nclosed within that rea. This fact determines the shape of the curve in Fig. I but not its displacement B. The latter is affected by a host of quantities including manual design time, automated design costs (DA j, etc. In particular, the larger the number of chips actually manufactured for any given design, the smaller B becomes. In addition, once chips start to come off the line, we must consider the cost of testing them. Finally, as chips get larger their yield goes down (unless there is some kind of redundancy scheme j, and the possibility of failure in subsequent life also increases with chip complexity. The net results of the comments above are that in today’s world we can get good value for our expenditures only if we make large quantities of any given chip. In practice, relatively few chips see the kind of widespread use that is necessary to make their cost really competitive. rhis arises because of engineering changes that are associated with design errors as well as with changes in philosophy as a machine is developed. The problem extends well past the release date of the machine because of late improvements, specific customer requirements, changes in philosophy, etc. This will be particularly true in the future with the coming emphasis on the translation of much of what is today’s software into firmware and the replacement of some of our current firmware with hardware. A major attempt to minimize this problem is the socalled “master slice” approach. In this scheme no chip is completely unique until after final metallization. Thus, the chip consists of an assemblage of unit-logic devices positioned where they are anticipated to be useful to each other. The final circuit is given its own specific H. FLEISHER AND L. I. MAISSEL IBM J . RES. DEVELOP. “personality” (or pattern of interconnections) via the top level of metallization. Such an approach is necessarily wasteful since it is impossible to optimize the placement of the unit-logic devices to suit all possible future circuits. This statement is supported by the fact that there are many master slice types available. These slices, of course, are then individually personalized into many more chip types. Is there, then, any situation in which a single chip, once designed, receives extended usage? The answer is ‘yes’ if we consider semiconductor memory technology. It is further worth noting that several features that are associated with large chips designed for memory are absent in random logic chips of comparable size. These include easy testability and redundancy. One therefore wonders whether some of the distinct advantages that memory technology enjoys over logic technology might not be applied to the latter. The intent to do this is a strong motivation for array logic. Array logic In this paper “array logic” is defined as the use of memory-like structures for performing logic. Array logic should not be confused with cellular or iterative arrays [ I ] which have a closer structural relation to masterslice approaches embodying random logic. Array logic functions by presenting the bits in the data path to the memory-like structures as “address bits.” Decoding of this address starts the process whereby a pre-determined result is extracted from the array. Because the functions generated by such an array depend only on the “personality” (i.e., bit content) of the array, logic can, in principle, be changed at the same rate at which memory can be written. The idea of performing logic in this manner is by no means new. Small lookup tables can be found in many of today’s machines and, in fact, the IBM 1620 worked in this fashion. We should also note that microcode, which has now become almost universal, is a form of lookup table, replacing conventional logic. The switch to microcode was dictated by considerations of cost rather than performance, as well as by the high frequency of change involved in the development of control logic. The latter is reflected in the growing popularity of writable control stores. Array logic is embodied in a memory-like structure wherein the variables are used as address bits and the output bits that have been selected are combined to yield a single bit which is the value of the function stored in the array for the particular combination of input bits. An associatively addressed memory array called Functional Memory [2] has been proposed as a substitute for conventional logic. However, this array had several deficiencies that become apparent later in this paper. MARCH 1975 Jnit cost Figure 1 Cost-performance curve for logic circuits. We now review some of the reasons why array logic was, until recently, insufficiently attractive to be widely adopted and discuss what has changed so as to make this picture rather different today.